High speed electronic components, such as semiconductor chips, are mounted on the front and back surfaces of planar circuit cards. Circuit paths, plated on the surfaces of the cards, electrically interconnect the components. Often there occurs a lack of surface area available for plating. Hence, each circuit card may be a multilayer circuit card in which a number of planar laminates, each carrying plated circuit paths, are laminated together. Electrical interconnections to the circuit paths internally of the laminates are made by plated through holes, holes which are drilled through the laminates and lined with plating which electrically joins circuit paths intercepted by the holes.
Plated circuits of each card are provided with pads, plated enlarged areas, on front and back surfaces adjacent one edge of the card which is to be plugged into a card edge connector. Electrical card edge terminals within the card edge connector frictionally engage the pads. The card edge terminals are secured in the base circuit board and may be electrically joined to plated circuit paths on the base circuit board. Additionally, the card edge terminals may include elongated post portions which project through the base circuit board to its opposite side for receiving wrapped wire connections.
Each card in an array of card edge connectors must be supplied with electrical power and ground return circuits. This can be accomplished by bus bars extending over the surface of the base circuit board, as shown in U.S. Pat. No. 3,725,843. As the number of circuit cards to be supplied by the bus bar increases, and as the density of circuit components on each card increases, the amount of current drawn from each bus bar increases accordingly. For example, in a typical large interconnection assembly, a large number of circuit cards will draw a cumulative total of 200 Amps or more from each bus bar. Each bus bar must have a cross section which is very large, in excess of an AWG #2 wire size, to provide adequate current carrying capacity. This requirement for size obviates the use of a bus bar which is stamped and formed from relatively thin metal strip. This requirement also eliminates incorporation of the bus bar into a card edge connector, since the sizes of and spacing between the card edge terminals in the connector are very small, in the order of one-tenth to one-sixteenth inches.
The high current carried by the bus bars, as well as voltage losses along with inductance effects of the bus bars would adversely affect the low signal voltages carried by the card edge terminals. Therefore, each bus bar must be isolated from, rather than incorporated into, the card edge connectors.
In the large interconnection assembly, connections for the multiple circuit cards are distributed along a bus bar and will cause a cumulative power drain and voltage drop. If conductors are interposed between the bus bar and each circuit card, additional voltage drops will occur due to contact resistances and bulk resistances of these conductors. Therefore, bus bar interconnections must compensate for cumulative power drain and must be designed for minimizing voltage drops due to additional resistance effects. Additional voltage losses are attributable to inductance effects. Voltage inductance losses are directly proportional to the rate of change of signal and the inductances of the bus bar and the conductors interposed between the bus bar and each circuit card. The rise times of the digital signals which are operative in each circuit card are measured in nanoseconds or fractions of nanoseconds. These short rise times will produce significant millivolt inductance drops. Therefore, bus bar interconnections must be designed for minimum millivolt reactance losses.